Design Methodology for ESD Power Supply Clamps in Advanced CMOS Technologies

Electrostatic Discharge (ESD) is one of the major reliability issues in advanced CMOS technologies. Research has shown that only I/O based ESD protection circuits are inadequate in providing necessary ESD protection. Therefore, it is important to have an effective ESD power supply clamp across the power supply rails so that the ESD event will be discharged through it and protects the circuit core. In this paper, we propose a design methodology for ESD power supply clamps in advanced CMOS technologies. The design methodology consists of four major steps: technology characterization, designing the circuit, simulation and measurement. Based on simulation and measurement results, the design is modified to improve performance. A static ESD power supply clamp in 65 nm CMOS technology is provided as a study case.